1. Field of the Invention
The present invention relates to a method for forming a gate structure with a local pulled-back conductive layer. In particular, a contact window that avoids the disadvantage of the prior art, such as short circuiting between the bit line contact and gate conductor (CBGC short), broken bit line contacts (CB open) and/or short circuiting of the bit line contacts (CBCB short), is formed.
2. Descriptions of the Related Art
A metal oxide semiconductor (MOS) device is normally composed of a metal layer, a silicon oxide layer, and a substrate. Because the adhesion between the metal and oxide is poor, a polysilicon material is often used as a substitution for metal when forming the conductive layer of an MOS device.
It is known that the resistance of a polysilicon material is higher than that of metal. Although impurities are doped onto the polysilicon layer for reducing resistance, the conductivity is still not high enough for good conductivity in a gate structure. Typically, a metal silicide layer, such as a tungsten silicide (WSi) layer, is added onto the polysilicon layer to improve the conductivity of the gate structure.
A contact window is formed alongside of the gate structure to form electrical connects between the metal layer of the bit line and substrate. A conventional method for forming a contact window will be described as follows. First, in reference to FIG. 1A, a substrate 102 is provided. A gate structure 103 is formed on the substrate 102, wherein the gate structure 103 comprises a first conductive layer 104, a second conductive layer 106, an insulation layer 108 and spacers 110. Then, a dielectric layer 112 is formed to cover the entire substrate 102 and gate structure 103. The first conductive layer 104 can be a polysilicon layer or an amorphous silicon layer, while the second conductive layer 106 can be a metal silicide layer.
In FIG. 1B, a selected portion of the dielectric layer 112 is removed by performing lithographic and etching processes until the surface of the substrate 102 has been exposed. As a result, a contact window 114 is formed. In FIG. 1C, a metal layer 116 is deposited over the dielectric layer 112, and the side walls and bottom of the contact window 114 to form a metal contact.
If the insulation layer 108 and the spacer 110 were overly etched due to improper control, the deposition of the metal layer would expose the second conductive layer 106 under the insulation layer 108. In addition, the second conductive layer 106 may be exposed if the second conductive layer 106 pierces the spacer 110 due to thermal strain caused by a subsequent thermal process. Thus, in reference to FIG. 1D, the exposed second conductive layer 106 connects to the metal layer 116 and forms an electrical connection 118 (as shown in the dotted line area) thereto, and thus, causes a short circuit between the bit line contact and gate conductor (CBGC short).
To solve the above-mentioned problem of an exposed second conductive layer 106, a method is disclosed in U.S. Pat. No. 5,989,987. In FIG. 2A, a substrate 202 is provided where a gate structure 203 is formed on the substrate 202. The gate structure 203 comprises a first conductive layer 204, a second conductive layer 206, and an insulation layer 208. The first conductive layer 204 can be a polysilicon layer or an amorphous silicon layer. Next, a pull back process is conducted by using an etchant to etch the second conductive layer 206, wherein the etchant is a mixture of NH4OH, H2O2 and H2O.
In FIG. 2B, spacers 210 are formed on the sides of the gate structure 203. Then, FIG. 2C shows a dielectric layer 212 that covers the entire substrate 202 and gate structure 203. A selected portion of the dielectric layer 212 is removed by performing lithographic process and etching processes to expose a portion of the surface of the substrate 202. As a result, a contact window 214 is formed.
In FIG. 2D, a metal layer 216 is formed to cover the dielectric layer 212 and the side walls and bottom of the contact window 214. In this way, a metal contact is formed.
In the method disclosed in U.S. Pat. No. 5,989,987, the second conductive layer 206 of the gate structure is etched globally. In other words, portions of the second conductive layer 206 that do not need to be removed for forming the contact window are also etched away. This etching is disadvantageous in several ways. First, because the second conductive layer 206 is oxidized and has an increased thickness during rapid thermal oxidation, the reduced space in the contact window can cause the bit line contact to break. Second, a short circuit between the bit line contacts may occur. This occurs when the space between the adjacent gate structures, not used for forming the contact window, are increased by the global etching. While the space is filled with a dielectric material, cavities may be formed in the dielectric material. Such cavities may be filled with conductive material when the conductive material is deposited into the contact windows for forming contact plugs. As a result, short circuiting may occur. Third, the resistance of the gate conductive is increased because the cross-sectional area of the conductive layer of the gate structure is reduced. Fourth, because the contact area between the first conductive layer 204 and the second conductive layer 206 is reduced, peeling will be induced in subsequent processes.
TW 544787 describes another method. First, FIG. 3A illustrates a substrate 302 in which the gate structures 303 are formed on the substrate 302. Each gate structure 303 comprises a first conductive layer 304, a second conductive layer 306 and an insulation layer 308, wherein the first conductive layer 304 can be a polysilicon layer or an amorphous silicon layer. A photoresist layer 309 is deposited over the substrate 302 and gate structures 303.
Next, FIG. 3B illustrates a bit line contact node mask or a bit line contact mask used to perform a lithographic and etching process to remove a portion of the photoresist layer 309 between the adjacent gate structures 303. As a result, an opening is formed. Then, an etching process is applied using an etchant to pull back the exposed second conductive layer 306.
In FIG. 3C, the photoresist layer 309 is removed and spacers 310 are formed on the sides of the gate structures 303. Then, in FIG. 3D, a dielectric layer 312 is formed to cover the substrate 302 and gate structures 303. Lithographic and etching processes are performed to remove a selected portion of the dielectric layer 312 to expose the substrate 302. In this way, a contact window 314 between adjacent gate structures 303 is formed.
Lastly, in reference to FIG. 3E, a metal layer 316 is formed to cover the dielectric layer 312 and the side walls and bottom of the contact window 314 to provide a metal contact.
As described above, the method of TW 544787 comprises a step of locally etching the second conductive layer 306 of the gate structure 303. Accordingly, the portion of the second conductive layer 306, on which a contact window is not going to be formed, will not be etched away. This method can solve the aforementioned problems, such as short circuiting between the bit line contacts and peeling. Nevertheless, the method of TW 544787 still has several disadvantages.
Specifically, in TW 544787, after the contact window is formed, the second conductive layer 306 will be oxidized during subsequent processes, such as rapid thermal oxidation, and will result in a thicker layer 306. A thickened layer 306 will decrease the space of the contact window and thus, causes a broken bit line contacts (CB open). Furthermore, the method has to increase the number of masks or change the thermal budget to provide additional patterns for the lithographic and etching process illustrated in FIG. 3B to pull-back the second conductive layer 306. Moreover, the lithographic and etching process illustrated in FIG. 3B involve a wet and high temperature procedure that is performed over a long period of time using a photoresist as the hard mask. However, the photoresist becomes relatively weak due to the exposure to high temperatures and moisture during the lengthy process. In other words, the photoresist can be easily damaged during high temperature and/or wet processes. Hence, the etchant used in the etching process may permeate into the gate structure along the interface between the photoresist and the gate structure, and thereby, etching others portions that need not to be etched.
Given the above descriptions, it is important to find an effective process that will not result in short circuiting between the bit line contact and gate conductor (CBGC short), a broken bit line contact (CB open) and/or short circuiting between the bit lines contacts (CBCB short) for gate structures with a pulled-back conductive layer.